The design and manufacturing process of an electronic circuit can be broadly divided into two stages, i.e., a pre-layout design stage and a post-layout design stage. Examples of the design and manufacturing process of electronic circuit may include, but are not limited to design of manufacturing processes of Integrated Circuits (IC), Printed circuit Boards (PCB), Micro Electro Mechanical Systems (MEMS), and Multi Chip Modules (MCM). In the pre-layout design stage a circuit design is transformed into a physical layout data. The physical layout data includes details of physical locations of the circuit elements, which are used in the design of an electronic circuit, on the electronic circuit. Thereafter, in the post-layout design stage, the physical layout data is converted into geometric layout design data, which is used for manufacturing the electronic circuit. The geometric layout design data is generated and stored in a number of data-format files. Examples of the input and output data-format files, may include, but are not limited to, Graphic Data System-II (GDSII™) data-format file, Open Artwork System Interchange Standard (OASIS), MEBES™, JEOL™, VSB-11/12™, OASIS-VSB™, Gerber™, Library Exchange Format/Design Exchange Format (LEF™/DEF™) and a proprietary data-format file which describes the geometric layout design data.
At post-layout design stage, large geometric layout design data is processed. Additionally, as post-layout design stage is the last stage before fabrication of the electronic circuit, therefore, it is essential that accurate and efficient operations are performed on geometric layout design data. The post-layout EDA applications are used to process geometric layout design data. A post-layout EDA application includes a plurality of components to process the geometrical layout design data. The plurality of components may include, but are not limited to data structures, operations, and external interfaces. A post-layout EDA application may be custom designed based on data-format file and target application usage by writing a new code for each component of the post-layout EDA application. Examples of the target application usage may include, but are not limited to, Mask Data Preparation (MDP), Design Rule Checker (DRC), Optical Proximity Collection (OPC), Resolution Enhancement Techniques (RET), Critical Area Analysis (CAA), Dummy Metal Filling, Mask Inspection, Mask/Manufacturing Rule Checker (MRC), Silicon Debugging, Compute Aided Design (CAD) Navigation, Layout Viewers, Layout Analysis and Failure Analysis. This enables efficient performance of a post-layout EDA application for the data-format file and the target application of the post-layout EDA application. Additionally, a post-layout EDA application may be developed using one or more components of existing post-layout EDA applications. This enables development of a stable post-layout EDA application at a reduced cost both in terms of effort and achieving stability and performance. However, a long time period is required to develop a stable post-layout EDA application that can processes the geometric layout design data efficiently with good performance without using one or more components of the existing post-layout EDA applications.
Some design databases, for example, OpenAccess™ and MilkyWay™ provide interoperability with a plurality of post-layout EDA applications through Application Programming Interfaces (APIs). These design databases enable the post-layout EDA application developers to write APIs for integration of a design database with one or more custom design post-layout EDA applications.
Further, the design databases and data-format files store the geometric layout design data in one or more of a flat representation and a hierarchical representation. The flat representation lists each geometrical figure of the geometrical layout design data. This requires large run-time memory for carrying out operations and on-disk memory for storage. The hierarchical representation includes a plurality of cells. A cell in the hierarchical representation includes references to zero or more cells and zero or more geometrical figures. The use of the hierarchical representation reduces the memory space required to store the geometric layout design data. However, implementing or performing some operation, such as, but not limited to spatial operations, on the hierarchical representation may be complex to implement and may be computationally expensive.
There is therefore, a need of a stable and efficient post-layout EDA application EDA Application development platform/toolkit that can interface with (read/write) a plurality of data-format files. Further, there is a need for a data representation of geometric layout design data that requires less memory and is suitable for performing various operations, such as, but not limited to, spatial operations, efficiently so that different target applications can be developed efficiently and quickly.